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BM63 Datasheet(PDF) 45 Page - Microchip Technology |
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BM63 Datasheet(HTML) 45 Page - Microchip Technology |
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45 / 56 page ![]() 2016 Microchip Technology Inc. Advance Information DS60001431A-Page 45 BM63 Figure 8-3 illustrates the timing diagram of the audio interface and Table 8-10 provides the timing specifica- tions. FIGURE 8-3: AUDIO INTERFACE TIMING DIAGRAM Note: Test Conditions: Slave mode, fs = 48 kHz, 24-bit data and SCLK0 period = 256 fs. TABLE 8-10: AUDIO INTERFACE TIMING SPECIFICATIONS PARAMETER SYMBOL MIN TYP MAX UNIT SCLK0 duty ratio dSCLK –50 – % SCLK0 cycle time tSCLKCY 50 – – ns SCLK0 pulse width high tSCLKCH 20 – – ns SCLK0 pulse width low tSCLKCL 20 – – ns RFS0 set-up time to SCLK0 rising edge tRFSSU 10 – – ns RFS0 hold time from SCLK0 rising edge tRFSH 10 – – ns DR0 hold time from SCLK0 rising edge tDH 10 – – ns |
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