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Start

Condition

Acknowledge Signal

from Receiver

Transmitter Stays off the

Bus During the

Acknowledge Clock

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP5521

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SNVS441H – JANUARY 2007 – REVISED MAY 2016

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7.5 Programming

7.5.1 I2C-Compatible Serial Bus Interface

7.5.1.1 Interface Bus Overview

The I2C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). These lines

should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (SCL).

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the high period of the clock the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 19. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a

stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following

sections provide further details of this process.

Figure 20. Acknowledge Signal

The Master device on the bus always generates the start and stop conditions (control codes). After a start

condition is generated, the bus is considered busy and it retains this status until a certain time after a stop

condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

start condition. A low-to-high transition of the SDA line while the SCL is high indicates a stop condition.

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