LP5521 datasheet(30/48 Pages) TI1

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LP5521

SNVS441H – JANUARY 2007 – REVISED MAY 2016

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7.6.2 Operation Mode Register (OP Mode)

Address 01H

Reset value 00H

Table 22. OP Mode Register

R_MODE[1]

R_MODE[0]

G_MODE[1]

G_MODE[0]

B_MODE[1]

B_MODE[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R_MODE

5:4

R/W

R channel operation mode

00b = Disabled

01b = Load program to SRAM, reset R channel PC

10b = Run program defined by R_EXEC

11b = Direct control

G_MODE

3:2

R/W

G channel operation mode

00b = Disabled

01b = Load program to SRAM, reset G channel PC

10b = Run program defined by G_EXEC

11b = Direct control

B_MODE

1:0

R/W

B channel operation mode

00b = Disabled

01b = Load program to SRAM, reset B channel PC

10b = Run program defined by B_EXEC

11b = Direct control

MODE registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to OP_MODE register

(01H) need to be longer than 153

μs (typ).

7.6.3 R Channel PWM Control (R_PWM)

Address 02H

Reset value 00H

Table 23. R PWM Register

R_PWM[7:0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R_PWM

7:0

R/W

R Channel PWM value during direct control operation mode

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