LP5521 datasheet(20/48 Pages) TI1

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SDA

SCL

START condition

STO

P condition

LP5521

SNVS441H – JANUARY 2007 – REVISED MAY 2016

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Programming (continued)

Figure 21. Start and Stop Conditions

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP5521 operates as a slave device with the 7-bit

address. The LP5521 I2C address is pin selectable from four different choices. If 8-bit address is used for

programming, the 8th bit is 1 for read and 0 for write. Table 9 shows the 8-bit I2C addresses.

Table 9. 8-Bit I2C Addresses

ADDR_SEL

[1:0]

I2C ADDRESS WRITE

(8 bits)

I2C ADDRESS READ

(8 bits)

0110 0100 = 64H

0110 0110 = 66H

0110 1000 = 68H

0110 1010 = 6AH

0110 0101 = 65H

0110 0111 = 67H

0110 1001 = 69H

0110 1011 = 6BH

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

sends an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a start condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

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