TLK105 datasheet(13/104 Pages) TI1

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MAC/

Switch

PCS

Signal

Process

PHY

AFE

Digital Loopback

PHY Digital

External Loopback

Analog Loopback

PCS Loopback

XFMR

MII Loopback

TLK105

TLK106

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SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016

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Hardware Configuration

(1)

Requires 100

Ω termination

3.9

Loopback Functionality

The TLK10x provides several options for Loopback that test and verify various functional blocks within the

PHY. Enabling loopback mode allows in-circuit testing of the TLK10x digital and analog data path.

Generally, the TLK10x may be configured to one of the Near-end loopback modes or to the Far-end

(reverse) loopback.

3.9.1

Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or

analog circuitry. The point at which the signal is looped back is selected using loopback control bits with

several options being provided. Figure 3-5 shows the PHY near-end loopback functionality.

Figure 3-5. Block Diagram, Near-End Loopback Mode

The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register

(BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at

address 0x0000, bit [14].

The Near-end Loopback can be selected according to the following:

•

Reg 0x0000, Bit [14]: MII Loopback

•

Reg 0x0016, Bit [0]: PCS input Loopback

•

Reg 0x0016, Bit [1]: PCS output Loopback

•

Reg 0x0016, Bit [2]: Digital Loopback

•

Reg 0x0016, Bit [3]: Analog Loopback

Table 3-5 describes the available operational modes for each loop mode:

Table 3-5. Loop Modes

LOOP MODE

MII

PCS INPUT

PCS

OUTPUT

DIGITAL

ANALOG(1)

EXTERNAL

Operational Setting

Force/ANEG 100/10

Force 100/10

Force 100

Force 10/100 ANEG

Force/ANEG 100/10

Operational MAC int.

MII Only

MII or RMII

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