OPA698 datasheet(24/27 Pages) TI

24 / 27 page

OPA698

SBOS258B

www.ti.com

A fine-scale output offset null, or DC operating point adjust-

ment, is often required. Numerous techniques are available

for introducing DC offset control into an op amp circuit. Most

of these techniques eventually reduce to adding a DC current

through the feedback resistor. In selecting an offset trim

method, one key consideration is the impact on the desired

signal path frequency response. If the signal path is intended

to be noninverting, the offset control is best applied as an

inverting summing signal to avoid interaction with the signal

source. If the signal path is intended to be inverting, applying

the offset control to the noninverting input may be consid-

ered. However, the DC offset voltage on the summing

junction will set up a DC current back into the source which

must be considered. Applying an offset adjustment to the

inverting op amp input can change the noise gain and

frequency response flatness. For a DC-coupled inverting

amplifier, Figure 25 shows one example of an offset adjust-

ment technique that has minimal impact on the signal fre-

quency response. In this case, the DC offsetting current is

brought into the inverting input node through resistor values

that are much larger than the signal path resistors. This will

insure that the adjustment circuit has minimal effect on the

loop gain as well as the frequency response.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with the high-frequency

OPA698 requires careful attention to layout design and

component selection. Recommended PCB layout techniques

and component selection criteria are:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Open a window in the ground and

power planes around the signal I/O pins, and leave the

ground and power planes unbroken elsewhere.

b) Provide a high quality power supply. Use linear regu-

lators, ground plane and power planes to provide power.

Place high frequency 0.1

µF decoupling capacitors < 0.2"

away from each power-supply pin. Use wide, short traces to

connect to these capacitors to the ground and power planes.

Also use larger (2.2

µF to 6.8µF) high-frequency decoupling

capacitors to bypass lower frequencies. They may be some-

what further from the device, and be shared among several

adjacent devices.

c) Place external components close to the OPA698. This

minimizes inductance, ground loops, transmission line ef-

fects and propagation delay problems. Be extra careful with

the feedback (RF), input and output resistors.

d) Use high-frequency components to minimize parasitic

elements. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter layout.

Metal film or carbon composition axially-leaded resistors can

also provide good performance when their leads are as short

as possible. Never use wirewound resistors for high-fre-

quency applications. Remember that most potentiometers

have large parasitic capacitances and inductances. Multi-

layer ceramic chip capacitors work best and take up little

space. Monolithic ceramic capacitors also work very well.

Use RF type capacitors with low ESR and ESL. The large

power pin bypass capacitors (2.2

µF to 6.8µF) should be

tantalum for better high frequency and pulse performance.

e) Choose low resistor values to minimize the time con-

stant set by the resistor and its parasitic parallel capacitance.

Good metal film or surface mount resistors have approxi-

mately 0.2pF parasitic parallel capacitance. For resistors

> 1.5k

Ω, this adds a pole and/or zero below 500MHz. Make

sure that the output loading is not too heavy. The recom-

mended 402

Ω feedback resistor is a good starting point in

most designs.

f) Use short direct traces to other wideband devices on

the board. Short traces act as a lumped capacitive load.

Wide traces (50 to 100 mils) should be used. Estimate the

total capacitive load at the output, and use the series isola-

tion resistor recommended in the typical performance curve,

RS vs Capacitive Load. Parasitic loads < 2pF may not need

the isolation resistor.

Ω

±200mV Output Adjustment

= –

= –2

Supply Decoupling

Not Shown

Ω

328

Ω

0.1

µF

500

Ω

20k

Ω

10k

Ω

0.1

µF

–5V

+5V

OPA698

+5V

–5V

FIGURE 25. DC-Coupled, Inverting Gain of –2, with Offset

Adjustment.

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