GS1672 datasheet(28/116 Pages) SEMTECH

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GS1672 HD/SD-SDI Serializer with Complete SMPTE

Audio & Video Support

Data Sheet

53623 - 6

July 2011

28 of 116

4.2 Parallel Data Inputs

Data signal inputs enter the device on the rising edge of PCLK, as shown in Figure 4-1.

Figure 4-1: GS1672 Video Host Interface Timing Diagrams

data_1

transition zone

data_1

data_0

transition zone

PCLK

PCLK period

DIN[19:0], F_DE,

H_HSYNC, V_VSYNC

data_0

SDR interface

Luma/Chroma* is launched on the positive edge of PCLK

by the source chip to the GS1672

TSU

Table 4-1: GS1672 Digital Input AC Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input data set-up time

tSU

50% levels;

1.8V operation

1.2

−−

Input data hold time

tIH

0.8

−−

Input data set-up time

tSU

50% levels;

3.3V operation

1.3

−−

Input data hold time

tIH

0.8

−−

Table 4-2: GS1672 Input Video Data Format Selections

Input Data Format

Pin/Register Bit Settings

DIN[9:0]

DIN[19:10]

20BIT

/10BIT

RATE

_SEL

SMPTE

_BYPASS

DVB_ASI

20-bit demultiplexed HD

format

HIGHLOW

Chroma

Luma

20-bit data Input

HD format

HIGH

LOW

DATA

20-bit demultiplexed SD

format

HIGHHIGHHIGHLOW

Chroma

Luma

20-bit data input

SD format

HIGHHIGH

LOW

DATA

10-bit multiplexed

HD format

LOW

HIGHLOW

High ImpedanceLuma/Chroma

10-bit data input

HD format

LOW

High ImpedanceDATA

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