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GS1672 Datasheet(PDF) 30 Page - Semtech Corporation

Part # GS1672
Description  HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support
PDF  116 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS1672 Datasheet(HTML) 30 Page - Semtech Corporation

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GS1672 HD/SD-SDI Serializer with Complete SMPTE
Audio & Video Support
Data Sheet
53623 - 6
July 2011
30 of 116
The GS1672 does not differentiate between a signal carrying video and a signal carrying
SDTI or HD-SDTI data in SD or HD formats. The user is responsible for ensuring that the
headers and data are not corrupted.
4.2.2 Parallel Input in DVB-ASI Mode
The GS1672 is in DVB-ASI mode when the SMPTE_BYPASS pin is set LOW, the DVB_ASI
pin is set HIGH, and the RATE_SEL0 pin is set HIGH. In this mode, all SMPTE processing
features are disabled.
When operating in DVB-ASI mode, the device must be set to 10-bit mode by setting the
20BIT/10BIT pin LOW. The device will accept 8-bit data words on DIN[17:10], where
DIN17 = HIN is the most significant bit of the encoded transport stream data and DIN10
= AIN is the least significant bit. In addition, DIN19 and DIN18 will be configured as the
DVB-ASI control signals INSSYNCIN and KIN respectively.
DIN19 = INSSYNCIN
DIN18 = KIN
DIN17~10 = HIN ~ AIN where AIN is the least significant bit of the transport stream data.
4.2.3 Parallel Input in Data-Through Mode
Data-Through mode is enabled when the SMPTE_BYPASS pin and the DVB_ASI pin are
LOW.
In this mode, data at the input bus is serialized without any encoding, scrambling or
word alignment taking place.
The input data width is controlled by the setting of the 20BIT/10BIT pin as shown in
Table 4-2 above.
NOTE:
When in HD 10-bit mode, asserting the SMPTE_BYPASS LOW to put the device
in SMPTE-BYPASS mode will create video errors. If the user desires to use the device as
a simple serializer in HD 10-bit mode, all video processing features may be disabled by
setting the IOPROC_EN/DIS pin LOW.
4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal of the GS1672 is determined by the input data
format and operating mode selection.
Table 4-3 below lists the input PCLK rates and input signal formats according to the
external selection pins for the GS1672.



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