PCI1520 datasheet(49/138 Pages) TI

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3−13

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

S/P = Start/Stop Condition

A = Slave Acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Figure 3−11. Serial-Bus Protocol − Byte Write

Figure 3−12 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command

bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1520 master must acknowledge reception

of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.

The SCL signal remains driven by the PCI1520 master.

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Sb6

b3 b2 b1 b0

Slave Address

S/P = Start/Stop Condition

M = Master Acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Start

Restart

R/W

A = Slave Acknowledgement

Stop

Figure 3−12. Serial-Bus Protocol − Byte Read

Figure 3−13 illustrates EEPROM interface doubleword data collection protocol.

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Data Byte 2

Data Byte 1

Data Byte 0

M = Master Acknowledgement

S/P = Start/Stop Condition

A = Slave Acknowledgement

Data Byte 3

Restart

R/W

Slave Address

Start

Figure 3−13. EEPROM Interface Doubleword Data Collection

3.6.3

Serial-Bus EEPROM Application

When the PCI bus is reset and the serial-bus interface is detected, the PCI1520 attempts to read the subsystem

identification and other register defaults from a serial EEPROM. The registers and corresponding bits that can be

loaded with defaults through the EEPROM are provided in Table 3−7.

PCI1520 Datasheet(PDF) 49 Page - Texas Instruments

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