PCI1520 datasheet(79/138 Pages) TI

79 / 138 page

4−17

Table 4−8. System Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

31−30†

SER_STEP

Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling

and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31 and 30 are

global to all PCI1520 functions.

00 = INTA/INTB signal in INTA/INTB IRQSER slots

01 = INTA/INTB signal in INTB/INTC IRQSER slots

10 = INTA/INTB signal in INTC/INTD IRQSER slots

11 = INTA/INTB signal in INTD/INTA IRQSER slots

29†

INTRTIE

Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are

signaled as INTA. INTA can then be shifted by using bits 31−30 (SER_STEP). This bit is global to all PCI1520

functions.

When configuring the PCI1520 functions to share PCI interrupts, multifunction terminal MFUNC3 must be

configured as IRQSER prior to setting the INTRTIE bit.

RSVD

Reserved. Bit 28 returns 0 when read.

27†

P2CCLK

P2C power switch clock. The PCI1520 CLOCK signal is used to clock the serial interface power switch and

the internal state machine. The default state for bit 27 is 0, requiring an external clock source provided to the

CLOCK terminal (terminal number F15 for the GHK package or terminal number 154 for the PDV package).

Bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal.

0 = CLOCK provided externally, input to PCI1520 (default)

1 = CLOCK generated by internal oscillator and driven by PCI1520.

SMIROUTE

SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled

when a write occurs to power a PC Card socket.

0 = PC Card power change interrupts routed to IRQ2 (default)

1 = A CSC interrupt is generated on PC Card power changes.

SMISTATUS

SMI interrupt status. This socket-dependent bit is set when bit 24 (SMIENB) is set and a write occurs to set

the socket power. Writing a 1 to bit 25 clears the status.

0 = SMI interrupt signaled (default)

1 = SMI interrupt not signaled

24†

SMIENB

SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt

signaling is enabled and generates an interrupt. This bit is shared and defaults to 0 (disabled).

RSVD

Reserved. Bit 23 returns 0 when read.

CBRSVD

CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus

terminals are driven low. When this bit is 0, these terminals are placed in a high-impedance state.

0 = Place CardBus RSVD terminals in a high-impedance state.

1 = Drive Cardbus RSVD terminals low (default).

VCCPROT

VCC protection enable. Bit 21 is socket dependent.

0 = VCC protection enabled for 16-bit cards (default)

1 = VCC protection disabled for 16-bit cards

REDUCEZV

Reduced zoomed video enable. When this bit is enabled, terminals A25−A22 of the card interface for PC

Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This

bit is encoded as:

0 = Reduced zoomed video disabled (default)

1 = Reduced zoomed video enabled

19−16

RSVD

Reserved. Do not change the default value.

15†

MRBURSTD

Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst

downstream.

0 = Downstream memory read burst is disabled.

1 = Downstream memory read burst is enabled (default).

14†

MRBURSTU

Memory read burst enable upstream. When bit 14 is set, the PCI1520 allows memory read transactions to

burst upstream.

0 = Upstream memory read burst is disabled (default).

1 = Upstream memory read burst is enabled.

SOCACTIV

Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and is

cleared upon read of this status bit. This bit is socket-dependent.

0 = No socket activity (default)

1 = Socket activity

RSVD

Reserved. Bit 12 returns 1 when read.

† This bit is global and is accessed only through function 0.

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