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QL8050 Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers |
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QL8050 Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers |
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22 / 49 page  ZZZTXLFNORJLFFRP 4XLFN/RJLF&RUSRUDWLRQ (FOLSVH,, )DPLO\ 'DWD 6KHHW5HY % Preliminary $& &KDUDFWHULVWLFV The AC Specifications (at VCC = 1.8 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16)) are provided from 7DEOH to 7DEOH . Logic Cell diagrams and waveforms are provided from )LJXUH to )LJXUH . )LJXUH (FOLSVH,, Logic Cell 7DEOH /RJLF &HOOV 6\PERO 3DUDPHWHU 9DOXH /RJLF&HOOV 0LQ 0D[ tPD Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output - 0.257 ns tSU Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.22 ns - tHL Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - tCO Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. - 0.255 ns tCWHI Clock High Time: required minimum time the clock stays high 0.46 ns - tCWLO Clock Low Time: required minimum time that the clock stays low 0.46 ns - tSET Set Delay: time between when the flip-flop is ”set” (high) and when the output is consequently “set” (high) - 0.18 ns tRESET Reset Delay: time between when the flip-flop is ”reset” (low) and when the output is consequently “reset” (low) - 0.09 ns tSW Set Width: time that the SET signal must remain high/low 0.3 ns - tRW Reset Width: time that the RESET signal must remain high/low 0.3 ns - |
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