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QL8050 Datasheet(PDF) 36 Page - List of Unclassifed Manufacturers

Part # QL8050
Description  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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QL8050 Datasheet(HTML) 36 Page - List of Unclassifed Manufacturers

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TDI/RSI
Test Data In for JTAG/RAM
init. Serial Data In
Hold HIGH during normal operation. Connects to serial PROM
data in for RAM initialization. Connect to VCC if unused
TRSTB/RRO
Active low Reset for
JTAG/RAM init. reset out
Hold LOW during normal operation. Connects to serial PROM
reset for RAM initialization. Connect to GND if unused
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VCC if not used
for JTAG
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to VCC or
ground if not used for JTAG
TDO/RCO
Test data out for JTAG/RAM
init. clock out
Connect to serial PROM clock for RAM initialization. Must be left
unconnected if not used for JTAG or RAM initialization
IO BANK A
IO BANK B
VCCIO (C)
INREF(C)
IOCTRL(C)
IO(C)
VCCIO(D)
INREF(D)
IOCTRL(D)
IO(D)
IO BANK F
IO BANK E
(H)
INREF(H)
IOCTRL(H)
IO(H)
VCCIO
VCCIO
(G)
INREF(G)
IOCTRL(G)
IO(G)



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