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QL8050 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers

Part # QL8050
Description  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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QL8050 Datasheet(HTML) 14 Page - List of Unclassifed Manufacturers

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Preliminary

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There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device.
Each Quad-Net is local to a quadrant. Before driving the columns clock buffers, the quad-net is
driven by the output of a mux which selects between the GCLK input and an internally generated
clock source (see
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Quad Net
GCLK Pin
Global Clock Net
tPGCK
tBGCK
Internally generated clock, or
clock from general routing network
Global Clock
(GCLK) Input
Global Clock Network
FF
Global Clock Buffer



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