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QL8050 Datasheet(PDF) 17 Page - List of Unclassifed Manufacturers |
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QL8050 Datasheet(HTML) 17 Page - List of Unclassifed Manufacturers |
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17 / 49 page  4XLFN/RJLF &RUSRUDWLRQ ZZZTXLFNORJLFFRP (FOLSVH,,)DPLO\ 'DWD 6KHHW 5HY % Preliminary -RLQW7HVW$FFHVV*URXS -7$* ,QIRUPDWLRQ )LJXUH -7$*%ORFN 'LDJUDP Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: • Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. • Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. TCK TMS TRSTB RDI TDO Instruction Decode & Control Logic Tap Controller State Machine (16 States) Instruction Register Boundary-Scan Register (Data Register) Mux Bypass Register Mux Internal Register I/O Registers User Defined Data Register |
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