AD8369 datasheet(14/24 Pages) AD

14 / 24 page

REV. 0

–14–

AD8369

out to pin CMDC for decoupling to ground. An external

capacitor from CMDC to COMM of 0.01

mF or more is

recommended to lower the input common-mode impedance of

the AD8369 and improve single-ended operation.

Signals must be ac-coupled at the input, either via a pair of

capacitors or a transformer. These may not be needed when the

source has no dc path to ground, such as a SAW filter. The

output may need dc blocking capacitors when driving dc-

grounded loads, but it can be directly coupled to an ADC,

provided that the common-mode levels are compatible.

The input and output resistances form a high-pass filter in com-

bination with any external ac-coupling capacitors that should

be chosen to minimize signal roll-off at low frequencies. For

example, using input-coupling capacitors of 0.1

mF, each driving

a 100

W input node (200 W differential), the –3 dB high-pass

corner frequency is at:

210

100

p()(

)

–

= kHz

It is important to note that the input and output resistances are

subject to process variations of up to

±20%. This will affect the

high-pass corner frequencies and the overall gain when driven

from, or loaded by, a finite impedance (see the Reducing Gain

Sensitivity to Input and Output Impedance Variation section).

Noise and Distortion

It is a common aspect of this style of VGAs, however imple-

mented, that the effective noise figure worsens as the gain is

reduced. The AD8369 uses a fixed gain amplifier, having a certain

invariant noise spectral density, preceded by an attenuator.

Thus, the noise figure increases simply by 6 dB per tap point,

from a starting point of 7 dB at full gain.

However, unlike voltage-controlled amplifiers that must neces-

sarily invoke nonlinear elements in the signal path, the distortion

in a step-gain amplifier can be very low and is essentially indepen-

dent of the gain setting. Note that the postamplifier 3 dB step

does not affect the noise performance, but it has some bearing

on the output third-order intercept (OIP3). See TPCs 3 and 9.

Offset Control Loop

The AD8369 uses a control loop to null offsets at the input. If

left uncorrected, these offsets, in conjunction with the gain of

the AD8369, would reduce the available voltage swing at the

output. The control loop samples the differential output volt-

age error and feeds nulling currents back into the input stage.

The nominal high-pass corner frequency of this loop is inter-

nally set to 520 kHz, but it is subject to process variations of

up to

±20%. This corner frequency can be reduced by adding

an external capacitor from the FILT pin to ground, in parallel

to an internal 30 pF capacitor. For example, an external capaci-

tor of 0.1

mF would lower the high-pass corner by a factor of

30/100,030, to approximately 156 Hz. This frequency should

be chosen to be at least one decade below the lowest compo-

nent of interest in the input spectrum.

Digital Control

The gain of the AD8369 is controlled via a serial or parallel

interface, as shown in Figure 2. Serial or parallel operation is

selected via the SENB pin. Setting SENB to a logic low (< VS/2)

selects parallel operation, while a logic high on SENB (> VS/2)

selects serial operation. The AD8369 has two control registers, the

gain control register and the shift register. The gain control register

is a latch that holds the data that sets the amplifier gain. The

shift registers are composed of four flip-flops that accept the

serial data stream.

DENB

SENB

MUX

SHIFT

BIT0

(DATA)

BIT1

(CLOCK)

BIT2

BIT3

GAIN CONTROL REGISTER

(LATCH)

TO GAIN CONTROL SECTION

BIT0

BIT1

BIT2

BIT3

Figure 2. Digital Interface Block Diagram

In parallel operation, the 4-bit parallel data is placed on pins

BIT3 through BIT0 and passed along to the gain control register

via the mux. Data is latched into the gain control register on the

falling edge of the input to DENB, subject to meeting the speci-

fied setup and hold times. If this pin is held high (> VS/2), any

changes in the parallel data will result in a change in the gain,

after propagation delays. This is referred to as the transparent

mode of operation. If DENB is held low, the last 4-bit word in

the gain control register will remain latched regardless of the signals

at the data inputs.

In serial operation, the BIT0 pin is used for data input while the

BIT1 pin is the clock input. Data is loaded into the serial shift

registers on the rising edge of the clock when DENB is low.

Given the required setup and hold times are observed, four rising

edge transitions of the clock will fully load the shift register. On

the rising edge of DENB, the 4-bit word in the shift register is

passed into the gain control register. While this pin is held high,

the clock input to the shift registers is turned off. Once DENB is

taken low, the shift register clock is again enabled and the last 4-bit

word prior to enabling the clock will be latched into the gain

control registers. This enables the loading of a new 4-bit gain

control word without interruption of the signal path. Only when

DENB goes high is data transferred from the shift registers to the

gain control registers. If no connections are made to the digital

control pins, internal 40 k

W resistors pull these pins to levels

that set the AD8369 to its minimum gain condition.

At power-up or chip enable, if the AD8369 is in parallel mode

and DENB is held low, the gain control register will come up in

an indeterminate state. To avoid this, DENB should be held

high with valid data present during power-up when operating in

the parallel mode. In serial mode, the data in the gain control

interface powers up with a random gain code independent of

the DENB pin. Serial mode operation requires at least four

clock cycles and the transition of DENB from low to high for

valid data to be present at the gain control register.

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