DS3134 datasheet(120/203 Pages) DALLAS

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DS3134

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Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only

bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be

read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set

to a one while the write is taking place. It will be set to zero once the write operation has completed.

RDMAC

0774h

5432

D15

D14

D13

D12

D11

D10

Note: Bits that are underlined are read only, all other bits are read-write.

Bits 0 to 15 / Receive DMA Configuration RAM Data (D0 to D15). Data that is written to or read

from the Receive DMA Configuration RAM.

8.2 TRANSMIT SIDE

8.2.1 OVERVIEW

The Transmit DMA uses a scatter gather technique to read packet data from main memory. The Host will

keep track of and decide where (and when) the DMA should grab the outgoing packet data from. There

are a set of descriptors that is handed back and forth between the Host and the DMA. Via the descriptors

the Host can inform the DMA where to obtain the packet data from and the DMA can tell the Host when

the data has been transmitted.

The operation of the Transmit DMA has three main areas as shown in Figures 8.2.1A and 8.2.1B and

Table 8.2.1A. The Host will write to the Pending Queue informing the DMA which channels have packet

data that is ready to be transmitted. Associated with each Pending Queue Descriptor is a data buffer that

contains the actual data payload of the HDLC packet. The data buffers can be between 1 and 8191 bytes

in length (inclusive). If an outgoing packet requires more than memory than a data buffer contains, then

the Host can link the data buffers to handle packets of any size.

The Done Queue Descriptors contain information that the DMA wishes to pass to the Host. The DMA

will write to the Done Queue when it has completed transmitting either a complete packet or data buffer

(see the discussion on DMA Update to the Done Queue below). Via the Done Queue Descriptors, the

DMA informs the Host about the status of the outgoing packet data.

If an error occurs in the

transmission, the Done Queue can be used by the Host to recover the packet data that did not get

transmitted and the Host can then re-queue the packets for transmission.

If enabled, the DMA can burst read the Pending Queue Descriptors and burst writes the Done Queue

Descriptors. This helps minimize PCI Bus accesses, freeing the PCI Bus up to do more time critical

functions. See Sections 8.2.3 and 8.2.4 for more details on this feature.

DS3134 Datasheet(PDF) 120 Page - Dallas Semiconductor