DS3134 datasheet(124/203 Pages) DALLAS

Part #	DS3134

Description	Chateau Channelized T1 And E1 And HDLC Controller

PDF	203 Pages

Scroll/Zoom	100%

Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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124 / 203 page

DS3134

124 of 203

Transmit DMA Memory Organization Figure 8.2.1B

Free Data Buffer Space

Transmit Pending Queue Descriptors:

Contains Index Pointers to Packet Descriptors

of Queued Data Buffers that are Ready

to be Transmitted

Pending Queue Base Address (32)

Pending Queue End Address (16)

Pending Queue Host Write Pointer (16)

Pending Queue DMA Read Pointer (16)

Up to 64K dwords

Free Queue Descriptors Allowed

Transmit Done Queue Descriptors:

Contains Index Pointers to Packet Descriptors

of Data Buffers that have been Transmitted

Done Queue Base Address (32)

Done Queue End Address (16)

Done Queue DMA Write Pointer (16)

Done Queue Host Read Pointer (16)

Up to 64K dwords

Done Queue Descriptors Allowed

Transmit Packet Descriptors:

Contains 32-Bit Addresses

to Data Buffers as well as

Status/Control Information and

Links to Other Packet Descriptors

Descriptor Base Address (32)

Up to 64K Quad dwords

Descriptors Allowed

Used Data Buffer Space

Main Offboard Memory

(32-Bit Address Space)

Internal Chateau Registers

dmatbd

DS3134 Datasheet(PDF) 124 Page - Dallas Semiconductor