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DM9161 Datasheet(PDF) 31 Page - List of Unclassifed Manufacturers |
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DM9161 Datasheet(HTML) 31 Page - List of Unclassifed Manufacturers |
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31 / 47 page ![]() DM9161 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Final 31 Version: DM9161-DS-F02 May 10,2002 When this bit is set, the link status change will not generate the interrupt 21.8 INTR mask 1, RW Master Interrupt Mask When this bit is set, no interrupts will be generated under any condition 21.7-21.5 Reserved 0, RO Reserved 21.4 FDX change 0,RO/LH Duplex Status Change Interrupt “1” indicates a change of duplex since last register read. A read of this register will clear this bit 21.3 SPD change 0, RO/LH Speed Status Change Interrupt “1” indicates a change of speed since last register read. A read of this register will clear this bit 21.2 LINK change 0, RO/LH Link Status Change Interrupt “1” indicates a change of link since last register read. A read of this register will clear this bit 21.1 Reserved 0, RO Reserved 21.0 INTR status 0, RO/LH Interrupt Status The status of MDINTR#. “1” indicates that the interrupt mask is off that one or more of the change bits are set. A read of this register will clear this bit 8.12 DAVICOM Specified Receive Error Counter Register (RECR) – 22 Bit Bit Name Default Description 22.15-0 Rcv_ Err_ Cnt 0, RO Receive Error Counter Receive error counter that increments upon detection of REER 8.13 DAVICOM Specified Disconnect Counter Register (DISCR) – 23 Bit Bit Name Default Description 23.15- 23.8 Reserved 0, RO Reserved 23.7-23.0 Disconnect Counter 0, RO Disconnect Counter that increments upon detection of disconnection 8.14 DAVICOM Hardware Reset Latch State Register (RLSR) – 24 Bit Bit Name Default Description 13 LH_LEDST 0 TXCLK pin reset latch value 12 LH_CSTS 0 CABLESTS pin reset latch value 11 LH_RMII 0 COL pin reset latch value 10 LH_SCRAM 1 RXCLK pin reset latch value 9 LH_REPTR 0 RXDV pin reset latch value 8 LH_TSTMOD 0 RXER pin reset latch value 7 LH_OP2 1 LINKLED pin reset latch value 6 LH_OP1 1 SPOLED pin reset latch value 5 LH_OP0 1 FDXLED pin reset latch value 4 LH_PH4 0 CRS pin reset latch value |
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