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DM9161 Datasheet(PDF) 36 Page - List of Unclassifed Manufacturers |
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DM9161 Datasheet(HTML) 36 Page - List of Unclassifed Manufacturers |
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36 / 47 page ![]() DM9161 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 36 Final Version: DM9161-DS-F02 May 10,2002 9.4.9 MII 100BASE-TX Receive Timing Diagram RXCLK t2 t1 tTX pd RXD [0:3], RXDV, RXER CRS RX+/- tRX S tRX h t4 t3 COL t5 t5 tRXc tRXh 9.4.10 MII 10BASE-T Nibble Transmit Timing Parameters Symbol Parameter Min. Typ. Max. Unit Conditions tTXs TXD[0:3), TXEN, TXER Setup To TXCLK High 5 --- --- ns tTXh TXD[0:3], TXEN, TXER Hold From TXCLK High 5 --- --- ns t1 TXEN Sampled To CRS Asserted --- 2 4 BT t2 TXEN Sampled To CRS De-asserted --- 15 20 BT tTXpd TXEN Sampled To 10TXO Out (Tx Latency) --- 2 4 BT 9.4.11 MII 10BASE-T Nibble Transmit Timing Diagram TXCLK tTX h t2 tTX S t1 tTX pd TXD [0:3], TXEN, TXER CRS 10TX+/- |
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