DM9161 datasheet(8/47 Pages) ETC

8 / 47 page

DM9161

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

Final

Version: DM9161-DS-F02

May 10,2002

5.2 Media Interface, 4 pins

Pin No.

Pin Name

I/O

Description

3,4

RX+

RX-

Differential Receive Pair

Differential data is received from the media

7,8

TX+

TX-

O Differential Transmit Pair/PECL Transmit Pair

Differential data is transmitted to the media in TP mode

5.3 LED Interface, 3 pins

Pin No.

Pin Name

I/O

Description

FDX

/COL LED#

/OP0

(U)

Full/Half Duplex LED

Active states indicate the full-duplex mode. Active states see LED

configuration

Full-Duplex/Collision LED: when bit 5 of register 16 is set high

Active states indicate the full-duplex mode or activity Collision LED when

in the half-duplex mode. Active states see LED configuration

OP0: (power up reset latch input)

This pin is used to control the forced or advertised operating mode of the

DM9161 according to the Table A. The value is latched into the DM9161

registers at power-up/reset

SPEED LED#

/OP1

(U)

Speed LED

Active states indicate the 100Mbps mode. Active states see LED

configuration

When bit 6 of Register 16 is set high, it controls the SPEED LED as

100Base-TX SD signal output. For debug only

OP1: (power up reset latch input)

This pin is used to control the forced or advertised operating mode of the

DM9161 according to the Table A. The value is latched into the DM9161

registers at power-up/reset

LINK

/ACT

LED#

/OP2

(U)

Link LED & Activity LED:

Active states indicate the good link for 10Mbps and 100Mbps operations.

It is also an active LED function when transmitting or receiving data.

Active states see LED configuration

OP2: (power up reset latch input)

This pin is used to control the forced or advertised operating mode of the

DM9161 according to the Table A. The value is latched into the DM9161

registers at power-up/reset

5.4 Mode, 2 pins

Pin No.

Pin Name

I/O

Description

PWRDWN

Power Down Control

Asserted high to force the DM9161 into power down mode. When in

power down mode, most of the DM9161 circuit block’s power is turned

off, only the MII management interface (MDC, MDIO) logic is available

(the PHY should respond to management transactions and should not

generate spurious signals on the MII)). To leave power down mode, the

DM9161 needs the hardware or software reset with the PWRDWN pin

low

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