DM9161 datasheet(14/47 Pages) ETC

14 / 47 page

DM9161

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

Final

Version: DM9161-DS-F02

May 10,2002

7.2 100Base-TX Operation

The 100Base-TX transmitter receives 4-bit nibble data

clocked in at 25MHz at the MII, and outputs a scrambled

5-bit encoded MLT-3 signal to the media at 100Mbps. The

on-chip clock circuit converts the 25MHz clock into a

125MHz clock for internal use.

The IEEE 802.3u specification defines the Media

Independent Interface. The interface specification defines

a dedicated receive data bus and a dedicated transmit

data bus.

These two busses include various controls and signal

indications that facilitate data transfers between the

DM9161 and the Reconciliation layer.

7.2.1 100Base-TX Transmit

The 100Base-TX transmitter consists of the functional

blocks shown in figure 7-3. The 100Base-TX transmit

section converts 4-bit synchronous data provided by the

MII to a scrambled MLT-3 125, a million symbols per

second serial data stream.

MII

Signals

MII

Interface/

Control

4B/5B

Encoder

4B/5B

Decoder

Code-

group

Alignment

Descrambler

Serial to

Parallel

NRZI

NRZ

CRM

MLT-3 to

NRZI

Adaptive

Digital

Logic

Scrambler

Parallel

to Serial

NRZ

NRZI

NRZI to

MLT-3

Driver

Rise/Fall

Time

CTL

TX CGM

LED

Driver

Collision

Detection

Carrier

Sense

Auto-

Negotiation

10BASE-T

Module

125M CLK

25M CLK

LED1-4#

25M OSCI

RXI+/-

10TXD+/-

100TXD+/-

Figure 7-3

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