Block Diagram

Operation

Basic Operation of the Current Mode Controlled

Switching Regulator

The main control loop includes the error amplifier, the current

amplifier and PWM comparator (as shown in

Figure 1). Dur-

ing heavy load or any load with FPWM mode enabled, the

controller is in constant frequency current mode operation:

the high-side switch is turned on at the beginning of each

clock cycle, and the output of the error amplifier is compared

with the sensed inductor current ramp; once the ramp

reaches the control level set by the error amplifier, the PWM

comparator reset the driver logic to turn off the high-side

switch; the low-side switch is turned on after certain delay

(the voltage at the SW pin is sensed and the low-side switch

is turned on once the SW pin voltage reaches zero. A preset

maximum delay is 100 ns). The low-side switch stays on until

the end of the cycle or until the inductor current reaches

zero; when this occurs, the zero cross detector will disable

the low-side driver to turn off the low-side switch. The zero

cross detector is disabled in FPWM mode.

For any peak current mode step-down converter, a compen-

sation ramp is needed to avoid subharmonic oscillations

DS100937-3

FIGURE 1. LM2631 Block Diagram

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