POWERED UP

HARDWARE

POWER-

DOWN

POWERED UP

POWERED UP

10+2 DATA BITS

10+2 DATA BITS

INVALID

DATA

VALID

DATA

EXTERNAL

EXTERNAL

S X X X X X 1 1

S

0 0

X

X

X

X

X

X X X X X

S

1 1

SOFTWARE

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

SETS SOFTWARE

POWER-DOWN

POWER-DOWN

POWERED UP

POWERED UP

DATA VALID

DATA VALID

INTERNAL

S X X X X X 1 0

S

0 0

X

X

X

X

X

S

MODE

DOUT

DIN

CLOCK

MODE

SETS INTERNAL

CLOCK MODE

SETS

POWER-DOWN

CONVERSION

CONVERSION

SSTRB

Figure 11a. Timing Diagram Power-Down Modes, External Clock

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock

+2.7V to +5.25V, Low-Power, 4-Channel,

Serial 10-Bit ADCs in QSOP-16

______________________________________________________________________________________

15

REFERENCE

BUFFER

REFERENCE-BUFFER

COMPENSATION

MODE

VREF

CAPACITOR

(µF)

POWER-DOWN

MODE

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

Disabled

—

—

Full

2

133

Enabled

Internal

—

Fast

5

26

Enabled

Internal

—

Full

300

26

Enabled

External

4.7

Fast

See Figure 13c

133

Enabled

External

4.7

Full

See Figure 13c

133

Disabled

—

—

Fast

2

133

Table 4. Typical Power-Up Delay Times