TMS320LC3x Interface

Figure 20 shows an application circuit to interface the

MAX1248/MAX1249 to the TMS320 in external clock

mode. The timing diagram for this interface circuit is

shown in Figure 21.

Use the following steps to initiate a conversion in the

MAX1248/MAX1249 and to read the results:

1) The TMS320 should be configured with CLKX

(transmit clock) as an active-high output clock and

CLKR (TMS320 receive clock) as an active-high

input clock. CLKX and CLKR on the TMS320 are

tied together with the MAX1248/MAX1249’s SCLK

input.

2) The MAX1248/MAX1249’s CS pin is driven low by

the TMS320’s XF_ I/O port, to enable data to be

clocked into the MAX1248/MAX1249’s DIN.

3) An 8-bit word (1XXXXX11) should be written to the

MAX1248/MAX1249 to initiate a conversion and

place the device into external clock mode. Refer to

Table 1 to select the proper XXXXX bit values for

your specific application.

4) The MAX1248/MAX1249’s SSTRB output is moni-

tored via the TMS320’s FSR input. A falling edge on

the SSTRB output indicates that the conversion is in

progress and data is ready to be received from the

MAX1248/MAX1249.

5) The TMS320 reads in one data bit on each of the

next 16 rising edges of SCLK. These data bits rep-

resent the 10 + 2-bit conversion result followed by

four trailing bits, which should be ignored.

6) Pull CS high to disable the MAX1248/MAX1249 until

the next conversion is initiated.

+2.7V to +5.25V, Low-Power, 4-Channel,

Serial 10-Bit ADCs in QSOP-16

20

______________________________________________________________________________________

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

MAX1248

MAX1249

MC683XX

SCK

PCS0

MOSI

MISO

CLOCK CONNECTIONS NOT SHOWN

1

µF

0.1

µF

0.1

µF

(GND)

ANALOG

INPUTS

+3V

+3V

CH0

CH1

CH2

CH3

COM

SHDN

VREF

SCLK

CS

DIN

SSTRB

DOUT

DGND

AGND

REFADJ

+2.5V

XF

CLKX

CLKR

DX

DR

FSR

CS

SCLK

DIN

DOUT

SSTRB

TMS320LC3x

MAX1249

Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface

Figure 19. MAX1248/MAX1249 QSPI Connections External Reference