CCU3000 datasheet(12/77 Pages) MICRONAS

12 / 77 page

CCU 3000, CCU 3000-I

CCU 3001, CCU 3001-I

MICRONAS INTERMETALL

Fig. 2–12: Using an external CPU

A0 ...A15

ROM/RAM

D0 ...D7

A15

XTAL1

XTAL2

CLK

Ext.

CPU

Emul.

RDY

Counter

2 in

clr

NMI

clr

A15

CCU

3000,

CCU

3001

EMU

Version

2.12. IM Bus Interface

The IM bus has been improved in its characteristics for

the CCU 3000, CCU 3001. In comparison to the inter-

face of the CCU 2000 series it differs in:

– multimaster ability

– 3 slave registers (8 bit wide)

– higher speed possible

The multimaster ability permits the use of several CCUs

on the same IM bus without impeding each other. Spe-

cially in add-on systems or systems with need of high

computing power and/or I/O requirements, this offers

great advantages. If several CCUs are admitted in a sys-

tem, it must be ascertained that these can communicate

with each other. A slave IM bus interface has been in-

stalled for this purpose. Parallel to the lines of the mas-

ter, three completely independent receiver registers

have been installed. All of these are constantly alert,

whether the master itself is active or not. As all CCUs

have the same IM bus addresses for these registers, the

contents of these registers (that is, for all CCUs that are

in the system) will be the same. The handshake

amongst these is realized in software, and one register

each is reserved for the device address, the request and

the data to be transported. The data rate can now be ad-

justed per software. It is possible to attain 1 MBit/s, if the

bus participants in question are devised to support this

rate. Also the actual realization of the bus can forbid

such a high data rate. The IM bus interface needs exter-

nal pull-up resistors.

In the I/O-page the IM bus interface reserves 8 bytes:

3 bytes

slave receiving registers (read)

1 byte

master address (write)

2 bytes

master data register (read/write)

1 byte

control register (read/write)

read:

bit 0

0... IM bus master ready

1... IM bus master busy

bit 1

1 Byte received in slave register 1

(may generate interrupt)

bit 2

IM-bus 1 control and status

(may generate interrupt)

bit 3

Word 3 Received (may generate

interrupt)

CCU3000 Datasheet(PDF) 12 Page - Micronas

CCU3000 Datasheet(HTML) 12 Page - Micronas

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