LAN9116 datasheet(83/109 Pages) MICROCHIP

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DS00002268A-page 83

LAN9116

5.5

PHY Registers

The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC

and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown

in Table 5-8, "LAN9116 PHY Control and Status Register"below.

5.5.1

BASIC CONTROL REGISTER

Note:

The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic

Control Register (Reset) is set.

TABLE 5-8:

LAN9116 PHY CONTROL AND STATUS REGISTER

PHY Control and Status Registers

Index

(In Decimal)

Basic Control Register

Basic Status Register

PHY Identifier 1

PHY Identifier 2

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Mode Control/Status Register

Special Modes Register

Special Control/Status Indications

Interrupt Source Register

Interrupt Mask Register

PHY Special Control/Status Register

Index (In Decimal):

Size:

16-bits

Bits

Description

Type

Default

Reset. 1 = software reset. Bit is self-clearing. For best results, when setting

this bit do not set other bits in this register.

RW/SC

Loopback. 1 = loopback mode, 0 = normal operation

Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is

enabled (0.12 = 1).

See Note 5-1

Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides

0.13 and 0.8) 0 = disable auto-negotiate process.

See Note 5-1

Power Down. 1 = General power down-mode, 0 = normal operation.

Note:

After this bit is cleared, the PHY may auto-negotiate with it's part-

ner station. This process may take a few seconds to complete.

Once auto-negotiation is complete, bit 5 of the PHY's Basic Status

Reserved

Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal

operation. Bit is self-clearing.

RW/SC

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