LAN9116 datasheet(92/109 Pages) MICROCHIP

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LAN9116

DS00002268A-page 92

 2005-2016 Microchip Technology Inc.

6.2

PIO Reads

PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are

latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-

formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between

cycles for the period specified.

PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles is identical with

the exception that D[31:16] are not driven during a 16-bit read.

Note:

Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.

FIGURE 6-1:

LAN9116 PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 32 bits with optional support for 16-bit bus widths

TABLE 6-3:

PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

165

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address Setup to nCS, nRD Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS

and nRD are deasserted. They may be asserted and deasserted in any order.

Data Bus

nCS, nRD

A[7:1]

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