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LAN9116 Datasheet(PDF) 97 Page - Microchip Technology |
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LAN9116 Datasheet(HTML) 97 Page - Microchip Technology |
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97 / 109 page ![]() 2005-2016 Microchip Technology Inc. DS00002268A-page 97 LAN9116 6.7 TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9116 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9116. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing charac- teristics as the address lines. Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-bit write. Note that address lines A[2:1] are still used when the LAN9116 is operating in 32-bit and 16-bit mode. Address bits A[7:3] are ignored. FIGURE 6-7: TX DATA FIFO DIRECT PIO WRITE TIMING Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths. TABLE 6-7: TX DATA FIFO DIRECT PIO WRITE TIMING Symbol Description MIN TYP MAX Units tcycle Write Cycle Time 165 ns tcsl nCS, nWR Assertion Time 32 ns tcsh nCS, nWR Deassertion Time 13 ns tasu Address, FIFO_SEL Setup to nCS, nWR Assertion 0 ns tah Address, FIFO_SEL Hold Time 0 ns tdsu Data Setup to nCS, nWR Deassertion 7 ns tdh Data Hold Time 0 ns Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. Data Bus nCS, nWR FIFO_SEL A[2:1] |
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