LAN8742A datasheet(30/124 Pages) MICROCHIP

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LAN8742A/LAN8742Ai

DS00001989A-page 30

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3.7

Configuration Straps

Configuration straps allow various features of the device to be automatically configured to user defined values. Config-

uration straps are latched upon Power-On Reset (POR) and pin reset (nRST). Configuration straps include internal

resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected

to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it

reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an

external resistor.

3.7.1

PHYAD[0]: PHY ADDRESS CONFIGURATION

The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into an internal register

at the end of a hardware reset (default = 0b). In a multi-PHY application (such as a repeater), the controller is able to

manage each PHY via the unique address. Each PHY checks each management data frame for a matching address in

the relevant bits. When a match is recognized, the PHY responds to that particular frame. The PHY address is also used

to seed the scrambler. In a multi-PHY application, this ensures that the scramblers are out of synchronization and dis-

perses the electromagnetic radiation across the frequency spectrum.

The device’s SMI address may be configured using hardware configuration to either the value 0 or 1. The user can con-

figure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can be

written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register.

The PHYAD0 hardware configuration strap is multiplexed with the RXER pin.

3.7.2

MODE[2:0]: MODE CONFIGURATION

The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-

serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is

then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,

the configuration of the 10/100 digital block is controlled by the register bit values and the MODE[2:0] configuration

straps have no affect.

The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-4. The user

may configure the transceiver mode by writing the SMI registers.

Note:

The system designer must guarantee that configuration strap pins meet the timing requirements specified

in Section 5.6.3, "Power-On nRST & Configuration Strap Timing". If configuration strap pins are not at the

correct voltage level prior to being latched, the device may capture incorrect strap values.

Note:

When externally pulling configuration straps high, the strap should be tied to VDDIO, except for REGOFF

and nINTSEL which should be tied to VDD2A.

TABLE 3-4:

MODE[2:0] BUS

MODE[2:0]

Mode Definitions

Default Register Bit Values

[13,12,10,8]

[8,7,6,5]

000

10BASE-T Half Duplex. Auto-negotiation disabled.

0000

N/A

001

10BASE-T Full Duplex. Auto-negotiation disabled.

0001

N/A

010

100BASE-TX Half Duplex. Auto-negotiation disabled.

CRS is active during Transmit & Receive.

1000

N/A

011

100BASE-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

1001

N/A

100

100BASE-TX Half Duplex is advertised. Auto-negoti-

ation enabled.

CRS is active during Transmit & Receive.

1100

0100

101

Repeater mode. Auto-negotiation enabled.

100BASE-TX Half Duplex is advertised.

CRS is active during Receive.

1100

0100

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