LAN9211 datasheet(33/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

3.7.2

Bus Reads

The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD

transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot

change during a sixteen bit read). No ordering requirements exist. The processor can access either

the low or high word first, as long as the next read is performed from the other word. If a read to the

same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The

LAN9211 will reset its read counters and restart a new cycle on the next read.

3.7.3

Mixed Endian Support

In order to allow flexibility with a range of designs, the LAN9211 supports mixed endian Data FIFO

accesses. The LAN9211 provides the ability to select Data FIFO endianess separately for accesses

through the Data FIFO ports (addresses 00h-3Ch) or using the FIFO_SEL input signal. This is

accomplished via the FPORTEND and FSELEND bits of the HW_CFG—Hardware Configuration

The FPORTEND bit determines the endianess of RX and TX Data FIFO host accesses made through

the Data FIFO port addresses (00h-3Ch). When FPORTEND is cleared, Data FIFO port accesses

utilize little endian byte ordering. When FPORTEND is set, Data FIFO port accesses utilize big endian

byte ordering.

The FSELEND bit determines the endianess of RX and TX Data FIFO host accesses when using the

FIFO_SEL signal. When FSELEND is cleared, FIFO_SEL accesses utilize little endian byte ordering.

When FSELEND is set, FIFO_SEL accesses utilize big endian byte ordering.

In addition to mixed endian support, the LAN9211 provides a word swap function, as described in

Section 3.7.4. The word swap function combined with the endianess select bits described above

determines how the Data/Status FIFO’s and CSR host access byte ordering is applied. Table 3.8

describes the various operation modes of the endianess and word swap ordering logic. Figure 3.9

illustrates the FIFO access byte ordering under various endianess and word swap settings. Refer to

Section 3.7.4 for additional details.

Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess

select bits.

3.7.4

Word Swap Function

In addition to mixed endian functionality, the LAN9211 supports a Word Swap Function. This feature

is controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD_SWAP—Word

Swap Control," on page 96. This register affects how words on the data bus are written to or read from

the Control and Status Registers and the Transmit and Receive Data/Status FIFOs.

Both the word swap function and the mixed endian control bits contain the ability to change the byte

ordering of host data path accesses. Figure 3.8 illustrates the order in which the word swap and

endianess select logic is applied within the LAN9211. Logically, the endian control logic is applied after

the word swap logic for write operations, and before the word swap logic for read operations.

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