LAN9211 datasheet(44/147 Pages) SMSC

44 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the

setting of PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the

LAN9211 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host

is required to check the READY bit and verify that it is set before attempting any other reads or writes

of the device. Before the LAN9211 is fully awake from this state the EDPWRDOWN bit in register 17

of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit

until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9211 is ready to resume normal

operation. At this time the WUPS field can be cleared.

Table 3.10 Power Management States

Device

BLOCK

(NORMAL OPERATION)

(WOL)

(ENERGY DETECT)

PHY

Full ON

Energy Detect Power-Down

MAC Power

Management

Full ON

RX Power Mgmt. Block

OFF

MAC and Host

Interface

Full ON

OFF

Internal Clock

Full ON

OFF

KEY

CLOCK ON

BLOCK DISABLED – CLOCK ON

FULL OFF

LAN9211 Datasheet(PDF) 44 Page - SMSC Corporation