LAN9211 datasheet(90/147 Pages) SMSC

90 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K

bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by

the host.

As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.

Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.

This is in addition to any TX data that may be queued in the TX data FIFO.

Conversely, as data is received by the LAN9211, it is moved from the MAC to the RX MIL FIFO, and

then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX

MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is

made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter

(RX_DROP) is incremented.

RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate

independent of the TX data and RX data and status FIFOs. FIFO levels set for the RX and TX data

and Status FIFOs do not take into consideration the MIL FIFOs.

5.3.10

RX_DP_CTRL—Receive Datapath Control Register

This register is used to discard unwanted receive frames.

Offset:

78h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes

the RX data FIFO to fast-forward to the start of the next frame. This bit will

remain high until the RX data FIFO fast-forward operation has completed.

No reads should be issued to the RX data FIFO while this bit is high.

Note:

Please refer to section “Receive Data FIFO Fast Forward” on

page 62 for detailed information regarding the use of RX_FFWD.

R/W

30-0

Reserved

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