LAN9211 datasheet(83/147 Pages) SMSC

83 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

5.3.4

INT_EN—Interrupt Enable Register

This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the

corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of

the interrupt source regardless of whether the source is enabled as an interrupt in this register.

Offset:

5Ch

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

Software Interrupt (SW_INT_EN)

R/W

30:26

Reserved

TX Stopped Interrupt Enable (TXSTOP_INT_EN)

R/W

RX Stopped Interrupt Enable (RXSTOP_INT_EN)

R/W

RX Dropped Frame Counter Halfway Interrupt Enable (RXDFH_INT_EN).

R/W

Reserved

TX IOC Interrupt Enable (TIOC_INT_EN)

R/W

RX DMA Interrupt (RXD_INT).

R/W

GP Timer (GPT_INT_EN)

R/W

PHY (PHY_INT_EN)

R/W

Power Management Event Interrupt Enable (PME_INT_EN)

R/W

TX Status FIFO Overflow (TXSO_EN)

R/W

Receive Watchdog Time-out Interrupt (RWT_INT_EN)

R/W

Receiver Error Interrupt (RXE_INT_EN)

R/W

Transmitter Error Interrupt (TXE_INT_EN)

R/W

12:11

Reserved

TX Data FIFO Overrun Interrupt (TDFO_INT_EN)

R/W

TX Data FIFO Available Interrupt (TDFA_INT_EN)

R/W

TX Status FIFO Full Interrupt (TSFF_INT_EN)

R/W

TX Status FIFO Level Interrupt (TSFL_INT_EN)

R/W

RX Dropped Frame Interrupt Enable (RXDF_INT_EN)

R/W

Reserved

RX Status FIFO Full Interrupt (RSFF_INT_EN)

R/W

RX Status FIFO Level Interrupt (RSFL_INT_EN)

R/W

2-0

GPIO [2:0] (GPIOx_INT_EN).

R/W

000

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