LAN9211 datasheet(85/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

5.3.7

RX_CFG—Receive Configuration Register

This register controls the LAN9211 receive engine.

Offset:

6Ch

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:30

RX End Alignment. This field specifies the alignment that must be

maintained on the last data transfer of a buffer. The LAN9211 will add

extra DWORDs of data up to the alignment specified in the table below.

The host is responsible for removing these extra DWORDs. This

mechanism can be used to maintain cache line alignment on host

processors.

Please refer to Table 5.2 for bit definitions

Note:

The desired RX End Alignment must be set before reading a

packet. The RX end alignment can be changed between reading

receive packets, but must not be changed if the packet is

partially read.

R/W

00b

29-28

Reserved

27-16

RX DMA Count (RX_DMA_CNT). This 12-bit field indicates the amount

of data, in DWORDS, to be transferred out of the RX data FIFO before

asserting the RXD_INT. After being set, this field is decremented for each

DWORD of data that is read from the RX data FIFO. This field can be

overwritten with a new value before it reaches zero.

R/W

000h

Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data

and status FIFOs of all pending data. When a ‘1’ is written, the RX data

and status pointers are cleared to zero.

Note:

Please refer to section “Force Receiver Discard (Receiver

Dump)” on page 62 for a detailed description regarding the use

of RX_DUMP.

14-13

Reserved

12-8

RX Data Offset (RXDOFF). This field controls the offset value, in bytes,

that is added to the beginning of an RX data packet. The start of the valid

data will be shifted by the number of bytes specified in this field. An offset

of 0-31 bytes is a valid number of offset bytes.

Note:

The two LSBs of this field (D[9:8]) must not be modified while

the RX is running. The receiver must be halted, and all data

purged before these two bits can be modified. The upper three

bits (DWORD offset) may be modified while the receiver is

running. Modifications to the upper bits will take affect on the

next DWORD read.

R/W

00000

7-0

Reserved

Table 5.2 RX Alignment Bit Definitions

[31]

[30]

End Alignment

4-byte alignment

16-byte alignment

32-byte alignment

Reserved

LAN9211 Datasheet(PDF) 85 Page - SMSC Corporation

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