LM5166DRCT datasheet(3/53 Pages) TI1

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ILIM

PGOOD

GND

VIN

HYS

ILIM

PGOOD

VOUT

GND

VIN

HYS

LM5166X, LM5166Y

Fixed Output Versions

LM5166

Adjustable Output Version

LM5166

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SNVSA67A – DECEMBER 2016 – REVISED DECEMBER 2016

Product Folder Links: LM5166

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(1)

P = Power, G = Ground, I = Input, O = Output.

5 Pin Configuration and Functions

VSON

10-Pin

Top View

Pin Functions

I/O(1)

DESCRIPTION

NUMBER

NAME

Switching node that is internally connected to the drain of the PFET buck switch (high side) and

the drain of the NFET synchronous rectifier (low side). Connect to the filter inductor.

VIN

Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to

input supply and input filter capacitor CIN. The path from the VIN pin to the input capacitor must be

as short as possible.

ILIM

Programming pin for current limit. Connecting the appropriate resistance from the ILIM pin to GND

selects one of the three current limit options. The available current limit options are detailed in

Table 3.

Programming pin for the soft-start delay. If a 100-kΩ resistor is connected from the SS pin to GND,

the internal soft-start circuit is disabled and the FB comparator reference steps immediately from

zero to full value when the regulator is enabled by the EN input. If the SS pin is left open, the

internal soft-start circuit ramps the FB reference from zero to full value in 900 µs. If a capacitor is

connected from the SS pin to GND, the soft-start time can be set longer than 900 µs.

Mode select and on-time programming pin for Constant On-Time control. Connect a resistor from

the RT pin to GND to program the on-time and hence switching frequency. Short RT to GND to

select PFM (pulse frequency modulation) operation.

PGOOD

Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low

when either FB or VOUT is not in regulation. Use a 10-kΩ to 100-kΩ pullup resistor to system

voltage rail or VOUT (no higher than 12 V).

Input pin of the precision enable / UVLO comparator. The regulator is enabled when the EN pin

voltage is greater than 1.22 V.

VOUT or FB

Feedback input to the voltage regulation loop. VOUT pin connects the internal feedback resistor

divider to the regulator output voltage for the fixed 3.3-V or 5-V options. FB pin connects the

internal feedback comparator to an external resistor divider for the adjustable voltage option. The

reference for the FB pin comparator is 1.223 V.

HYS

Drain of internal NFET that is turned off when the EN input is greater than the EN pin threshold.

External resistors from HYS to EN and GND program the input UVLO threshold and hysteresis.

GND

Regulator ground return.

PAD

Connect to GND pin and system ground on PCB. Path to CIN must be as short as possible.

LM5166DRCT Datasheet(PDF) 3 Page - Texas Instruments

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