 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LAN89730 Datasheet(PDF) 203 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
LAN89730 Datasheet(HTML) 203 Page - Microchip Technology |
|
|
203 / 218 page  2013-2015 Microchip Technology Inc. DS60001348A-page 203 LAN89730 7.6.6 MII INTERFACE TIMING This section specifies the MII interface transmit and receive timing. Note 7-12 Timing was designed for a system load between 10 pf and 25 pf. Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for additional MII timing information. FIGURE 7-6: MII TRANSMIT TIMING TABLE 7-19: MII TRANSMIT TIMING VALUES Symbol Description Min Max Units Notes tclkp TXCLK period 40 ns tclkh TXCLK high time tclkp*0.4 tclkp*0.6 ns tclkl TXCLK low time tclkp*0.4 tclkp*0.6 ns tval TXD[3:0], TXEN output valid from rising edge of TXCLK 22.0 ns Note 7-12 tinvld TXD[3:0], TXEN output invalid from rising edge of TXCLK 0ns Note 7-12 TXCLK (INPUT) TXD[3:0] (OUTPUT) TXEN (OUTPUT) tclkh tclkl tclkp tval tinvld tval tval tinvld |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
