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LAN89730 Datasheet(PDF) 204 Page - Microchip Technology |
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LAN89730 Datasheet(HTML) 204 Page - Microchip Technology |
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204 / 218 page  LAN89730 DS60001348A-page 204 2013-2015 Microchip Technology Inc. Note 7-13 Timing was designed for a system load between 10 pf and 25 pf. FIGURE 7-7: MII RECEIVE TIMING TABLE 7-20: MII RECEIVE TIMING VALUES Symbol Description Min Max Units Notes tclkp RXCLK period 40 ns tclkh RXCLK high time tclkp*0.4 tclkp*0.6 ns tclkl RXCLK low time tclkp*0.4 tclkp*0.6 ns tsu RXD[3:0], RXDV setup time to rising edge of RXCLK 8.0 ns Note 7-13 thold RXD[3:0], RXDV hold time after rising edge of RXCLK 9.0 ns Note 7-13 RXCLK (INPUT) tsu RXD[3:0] (INPUT) RXDV, RXER (INPUT) tclkh tclkl tclkp thold tsu thold thold tsu thold |
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