LAN89730 datasheet(207/218 Pages) MICROCHIP

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 2013-2015 Microchip Technology Inc.

DS60001348A-page 207

LAN89730

7.7.2

100 µW 25 MHZ CRYSTAL SPECIFICATIONS

When utilizing a 100 µW 25 MHz crystal, the following circuit design (Figure 7-10) and specifications (Table 7-23) are

required to ensure proper operation.

Note 7-14

The maximum allowable values for frequency tolerance and frequency stability are application

dependent. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the

combination of these two values must be approximately +/-45 PPM (allowing for aging).

Note 7-15

Frequency Deviation Over Time is also referred to as Aging.

Note 7-16

The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as +/-50 PPM.

Note 7-17

This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in

this value. The XO/XI pin and PCB capacitance values are required to accurately calculate the value

of the two external load capacitors. These two external load capacitors determine the accuracy of the

25.000 MHz frequency.

FIGURE 7-10:

100 µW 25 MHZ CRYSTAL CIRCUIT

TABLE 7-23:

100 µW CRYSTAL SPECIFICATIONS

Parameter

Symbol

Min.

Nom.

Max.

Unit

Note

Crystal Cut

AT, typ

Crystal Oscillation Mode

Fundamental Mode

Crystal Calibration Mode

Parallel Resonant Mode

Frequency

Ffund

25.000

MHz

Frequency Tolerance @ 25oCFtol

+/-50

PPM

Note 7-14

Frequency Stability Over Temp

Ftemp

+/-50

PPM

Note 7-14

Frequency Deviation Over Time

Fage

+/-3 to 5

PPM

Note 7-15

Total Allowable PPM Budget

+/-50

PPM

Note 7-16

Shunt Capacitance

Load Capacitance

Drive Level

100

µW

Equivalent Series Resistance

Ohm

XO Series Resistor

495

500

505

Ohm

Operating Temperature Range

-40

+105

XI Pin Capacitance

3 typ

Note 7-17

XO Pin Capacitance

3 typ

Note 7-17

LAN89730

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