MCP1810 datasheet(17/32 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005623A-page 17

MCP1810

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

3.1

Ground Pin (GND)

For optimal noise and power supply rejection ratio

(PSRR) performance, the GND pin of the LDO should

be tied to an electrically quiet circuit ground. This will

help the LDO power supply rejection ratio and noise

performance. The GND pin of the LDO conducts only

ground current, so a heavy trace is not required. For

applications that have switching or noisy inputs, tie the

GND pin to the return of the output capacitor. Ground

planes help lower the inductance and voltage spikes

caused by fast transient load currents.

3.2

Regulated Output Voltage Pin

(VOUT)

The VOUT pin is the regulated output voltage of the

LDO. A minimum output capacitance of 1.0 µF is

required for LDO stability. The MCP1810 is stable with

ceramic,

tantalum

and

aluminum-electrolytic

capacitors. See Section 4.2 “Output Capacitor” for

output capacitor selection guidance.

3.3

Feedback Pin (FB)

The output voltage is connected to the FB input. This

sets the output voltage regulation value.

3.4

Input Voltage Supply Pin (VIN)

Connect the unregulated or regulated input voltage

source to VIN. If the input voltage source is located

several inches away from the LDO, or the input source

is a battery, it is recommended that an input capacitor

be used. A typical input capacitance value of 1 µF to

10 µF should be sufficient for most applications (2.2 µF,

typical). The type of capacitor used can be ceramic,

tantalum, or aluminum-electrolytic. However, the low

ESR characteristics of the ceramic capacitor will yield

better noise and PSRR performance at high frequency.

3.5

Shutdown Control Input (SHDN)

The SHDN input is used to turn the LDO output voltage

on and off. When the SHDN input is at a logic-high

level, the LDO output voltage is enabled. When the

SHDN input is pulled to a logic-low level, the LDO

output voltage is disabled. When the SHDN input is

pulled low, the LDO enters a low-quiescent current

shutdown state, where the typical quiescent current is

1nA.

3.6

Exposed Thermal Pad (EP)

The 2x2 VDFN 8-Lead package has an exposed

thermal pad on the bottom of the package. The

exposed thermal pad gives the device better thermal

characteristics by providing a good thermal path to

either the printed circuit board (PCB) or heat sink, to

remove heat from the device. The exposed pad of the

package is at ground potential.

TABLE 3-1:

PIN FUNCTION TABLE

MCP1810

2x2 VDFN

Name

Description

GND

Ground

2VOUT

Regulated Output Voltage

3, 4, 5

Not connected pins (should either be left floated or connected to ground)

Output Voltage Feedback Input

7VIN

Input Voltage Supply

SHDN

Shutdown Control Input (active-low)

9EP

Exposed Thermal Pad, connected to GND

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