MCP1810 datasheet(19/32 Pages) MICROCHIP

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DS20005623A-page 19

MCP1810

4.0

DEVICE OVERVIEW

The MCP1810 is a 150 mA/100 mA output current, low

dropout (LDO) voltage regulator. The low dropout

voltage of 380 mV maximum at 150 mA of current

makes it ideal for battery-powered applications. The

input voltage ranges from 2.5V to 5.5V. The MCP1810

adds a shutdown-control input pin and is available in

six standard fixed-output voltage options: 1.2V, 1.8V,

2.5V, 3.0V, 3.3V and 4.2V. It uses a proprietary voltage

reference and sensing scheme to maintain the

ultra-low 20 nA quiescent current.

4.1

Output Current and Current

Limiting

The MCP1810 LDO is tested and ensured to supply a

minimum of 150 mA of output current for the

1.2V-to-3.5V output range, and 100 mA of output

current for the 3.5V-to-4.2V output range. The device

has no minimum output load, so the output load current

can go to 0 mA and the LDO will continue regulating

the output voltage within the specified tolerance.

The MCP1810 also incorporates an output current limit.

The current limit is set to 350 mA typical for the

1.2V

 VR ≤ 3.5V range, and to 250 mA typical for the

3.5V

 VR  5.5V range.

4.2

Output Capacitor

The MCP1810 requires a minimum output capacitance

of 1 µF for output voltage stability. Ceramic capacitors

are recommended because of their size, cost and

robust environmental qualities.

Aluminum-electrolytic and tantalum capacitors can be

used on the LDO output as well. The output capacitor

should be located as close to the LDO output as is

practical. Ceramic materials X7R and X5R have low

temperature coefficients and are well within the

acceptable ESR range required. A typical 1 µF X7R

0805 capacitor has an ESR of 50 m

.

For extreme output currents - below 100 µA or close to

150 mA/100 mA - an output capacitor with higher ESR

(tantalum, aluminum-electrolytic) is recommended.

Ceramic output capacitor may be used if a 0.5

 to 1

resistor is placed in series with the capacitor.

4.3

Input Capacitor

Low input-source impedance is necessary for the LDO

output to operate properly. When operating from

batteries, or in applications with long lead length

(> 10 inches) between the input source and the LDO,

some input capacitance is recommended. A minimum

of 1.0 µF to 4.7 µF of capacitance is recommended for

most applications.

For

applications

that

have

output

step

load

requirements, the input capacitance of the LDO is very

important.

The

input

capacitance

provides

low-impedance source of current for the LDO to use for

dynamic load changes. This allows the LDO to respond

quickly to the output load step. For good step-response

performance, the input capacitor should be equivalent

or higher value than the output capacitor. The capacitor

should be placed as close to the input of the LDO as is

practical. Larger input capacitors will also help reduce

any high-frequency noise on the input and output of the

LDO, as well as the effects of any inductance that

exists between the input source voltage and the input

capacitance of the LDO.

4.4

Shutdown Input (SHDN)

The SHDN input is an active-low input signal that turns

the LDO on and off. The SHDN threshold is a

percentage of the input voltage. The maximum

input-low logic level is 30% of VIN and the minimum

high logic level is 70% of VIN.

On the rising edge of the SHDN input, the shutdown

circuitry has a 20 ms (typical) delay before allowing the

LDO output to turn on. This delay helps to reject any

false turn-on signal or noise on the SHDN input signal.

After the 20 ms delay, the LDO output enters its

current-limited soft-start period as it rises from 0V to its

final regulation value. If the SHDN input signal is pulled

low during the 20 ms delay period, the timer will be

reset and the delay time will start over again on the next

rising edge of the SHDN input. The total time from the

SHDN input going high (turn-on) to the LDO output

being in regulation is typically 20 ms. Figure 4-1 shows

a timing diagram of the SHDN input.

FIGURE 4-1:

Shutdown Input Timing

Diagram.

SHDN

VOUT

20 ms

10 µs

TOR

20 ns (typical)

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