AD7616

Data Sheet

Rev. 0 | Page 48 of 50

SEQUENCER STACK REGISTERS

Although the channel register defines the next channel for conversion (be it a diagnostic channel or pair of analog input channels), to

sample numerous analog input channels, the 32 sequencer stack registers offer a convenient solution. Within the communication register,

when the REGADDR5 bit is set to Logic 1, the contents of REGADDR[4:0] specifies 1 of the 32 sequencer stack registers. Within each

sequencer stack register, the user can define a pair of analog inputs to sample simultaneously.

The structure of the sequence forms a stack, in which each row represents two channels to convert simultaneously. The sequence begins

with Sequencer Stack Register 1 and cycles through to Sequencer Stack Register 32. If Bit D8 (the enable bit, SSRENx) within a sequencer

stack register is set to 1, the sequence ends with the pair of analog inputs defined by that register, then returns to the first sequencer stack

register, and resumes the cycle again. By default, the sequencer stack registers are programmed to cycle through Channel V0A and

Channel V0B to Channel V7A and Channel V7B. After a full or partial reset is issued, the sequencer stack register reinitializes to cycle

through Channel V0A and Channel V0B to Channel V7A and Channel V7B.

Address: 0x20 to 0x3F, Reset: 0x0000, Name: Sequencer Stack Registers[0:31]

Table 27. Bit Descriptions for Sequencer Stack Registers[0:31]

Bits

Bit Name

Settings

Description

Reset

Access

[15:9]

Addressing

Bits[15:9] define the address of the relevant register. See the Addressing Registers

section for further details.

0x0

R/W

8

SSREN[0:31]

Setting this bit to 0 instructs the ADC to move to the next layer of the sequencer

stack after converting the present channel pair. Setting this bit to 1 defines that

layer of the sequencer stack as the final layer in the sequence. Thereafter, the

sequencer loops back to the first layer of the stack.

0x0

R/W

[7:4]

BSEL[0:31]

Channel selection bits for ADC B channels.

R/W

0000

V0B.

0001

V1B.

0010

V2B.

0011

V3B.

0100

V4B.

0101

V5B.

0110

V6B.

0111

V7B.

1000

V

1001

ALDO.

1010

Reserved.

1011

Set the dedicated bits for digital interface communication self test function. When

the conversion codes is read, Code 0xAAAA is read out as the conversion code of

Channel A, and Code 0x5555 is output as the conversion code of Channel B.

1100

Reserved.

[3:0]

ASEL[0:31]

Channel selection bits for ADC A channels. Settings are the same as for ADC B.

R/W

remaining 24 layers of the stack are reinitialized to 0x0.

Channel Selection bits for Set-A Channels

Defines final layer of s tack

Channel Selection bits for Set-B Channels

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

0

12

0

13

0

14

0

15

0

[15:9] Addressing (R/W)

[3:0] ASELx (R/W)

[8] SSRENx (R/W)

[7:4] BSELx (R/W)