Si511 datasheet(6/26 Pages) SILABS

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Si510/511

Rev. 1.2

Table 3. Output Clock Levels and Symmetry

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

CMOS Output Logic

High

VOH

0.85 x VDD

——

CMOS Output Logic

Low

VOL

—

0.15 x VDD

CMOS Output Logic

High Drive

IOH

3.3 V

–8

—

2.5 V

–6

—

1.8 V

–4

—

CMOS Output Logic

Low Drive

IOL

3.3 V

—

2.5 V

—

1.8 V

—

CMOS Output Rise/Fall

Time

(20 to 80% VDD)

TR/TF

0.1 to 212.5 MHz,

CL = 15 pF

0.45

0.8

1.2

0.1 to 212.5 MHz,

CL = no load

0.3

0.6

0.9

LVPECL Output

Rise/Fall Time

(20 to 80% VDD)

TR/TF

100

—

565

HCSL Output Rise/Fall

Time (20 to 80% VDD)

TR/TF

100

—

470

LVDS Output Rise/Fall

Time (20 to 80% VDD)

TR/TF

350

—

800

LVPECL Output

Common Mode

VOC

 to VDD – 2 V,

single-ended

—VDD –

1.4 V

—V

LVPECL Output Swing

 to VDD – 2 V,

single-ended

0.55

0.8

0.90

VPPSE

LVDS Output Common

Mode

VOC

100

 line-line

VDD = 3.3/2.5 V

1.13

1.23

1.33

100

 line-line, VDD = 1.8 V

0.83

0.92

1.00

LVDS Output Swing

Single-ended, 100

differential

termination

0.25

0.35

0.45

VPPSE

HCSL Output Common

Mode

VOC

to ground

0.35

0.38

0.42

HCSL Output Swing

Single-ended

0.58

0.73

0.85

VPPSE

Duty Cycle

All formats

485052

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