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Si511 Datasheet(PDF) 1 Page - Silicon Laboratories |
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Si511 Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 26 page  Rev. 1.2 7/15 Copyright © 2015 by Silicon Laboratories Si510/511 Si510/511 C RYSTAL O SCILLATOR (XO) 100 kH Z TO 250 MH Z Features Applications Description The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si510/511 uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this range. This IC-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. In addition, this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factory- configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. Functional Block Diagram Supports any frequency from 100 kHz to 250 MHz Low jitter operation 2 to 4 week lead times Total stability includes 10-year aging Comprehensive production test coverage includes crystal ESR and DLD On-chip LDO regulator for power supply noise filtering 3.3, 2.5, or 1.8 V operation Differential (LVPECL, LVDS, HCSL) or CMOS output options Optional integrated 1:2 CMOS fanout buffer Runt suppression on OE and power on Industry standard 5 x 7 and 3.2x 5 mm packages Pb-free, RoHS compliant –40 to 85 oC operation SONET/SDH/OTN Gigabit Ethernet Fibre Channel/SAS/SATA PCI Express 3G-SDI/HD-SDI/SDI Telecom Switches/routers FPGA/ASIC clock generation VDD Any-Frequency 0.1 to 250 MHz DSPLL ® Synthesis Fixed Frequency Oscillator CLK+ CLK– OE GND Low Noise Regulator Ordering Information: See page 14. Pin Assignments: See page 12. Si5602 1 2 3 6 5 4 GND OE VDD CLK+ CLK– NC 1 2 3 6 5 4 GND NC VDD CLK+ CLK– OE Si510(LVDS/LVPECL/HCSL/ Dual CMOS) Si510 (CMOS) Si511(LVDS/LVPECL/HCSL/ Dual CMOS) 1 2 4 3 GND VDD CLK OE 1 2 3 6 5 4 GND NC VDD CLK+ CLK– OE |
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