Si510/511

12

Rev. 1.2

2. Pin Descriptions

*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.

Table 11. Si510 Pin Descriptions (CMOS)

Pin

Name

CMOS Function

1

OE

Output Enable. Includes internal pull-up for OE active high. Includes

internal pull-down for OE active low. See ordering information.

2

GND

Electrical and Case Ground.

3

CLK

Clock Output.

4

Power Supply Voltage.

Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)

Pin

Name

LVPECL/LVDS/HCSL Function

1

NC

No connect. Make no external connection to this pin.

2

OE

Output Enable. Includes internal pull-up for OE active high. Includes

internal pull-down for OE active low. See ordering information.

3

GND

Electrical and Case Ground.

4

CLK+

Clock Output.

5

CLK–

Complementary Clock Output.

6

Power Supply Voltage.

Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)

Pin

Name

LVPECL/LVDS/HCSL Function

1

OE

Output Enable. Includes internal pull-up for OE active high. Includes

internal pull-down for OE active low. See ordering information.

2

NC

No connect. Make no external connection to this pin.

3

GND

Electrical and Case Ground.

4

CLK+

Clock Output.

5

CLK–

Complementary Clock Output.

6

Power Supply Voltage.

1

2

3

6

5

4

GND

OE

CLK+

CLK–*

NC

1

2

3

6

5

4

GND

NC

CLK+

CLK–*

OE

Si510 (CMOS)

Si510 (LVDS/LVPECL/HCSL/Dual CMOS*)

Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)

1

2

4

3

GND

CLK

OE