2.8 R5 REGISTER

The R5 Register is used to setup and control the FastLock circuitry for the RF synthesizer.

Reg

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9876543210

DATA[20:0]

C2

C1

C0

R5

0

RF_

CSR[1:0]

RF_

OM[1:0]

RF_

CPF[1:0]

RF_TOC[13:0]

1

0

1

2.8.1 RF_TOC[13:0] — FastLock Timeout Counter, RF Synthesizer

The RF_TOC[13:0] word controls the operation of the RF FastLock circuitry as well as the function of the FLoutRF output pin.

When RF_TOC is set to a value between 0 and 3, the RF timeout counter is disabled and the FLoutRF pin operates as a general

purpose I/O pin. When RF_TOC is set to a value between 4 and 16383, the RF FastLock mode is enabled and FLoutRF is utilized

as the RF FastLock output pin. The value programmed into RF_TOC represents the number of phase comparison cycles that the

RF synthesizer will spend in the FastLock state.

RF_TOC[13:0]

FastLock Mode

FastLock Period

[CP Events]

FLoutRF Pin Functionality

0

Disabled

N/A

High Impedance

1

Disabled

N/A

Logic LOW State

2

Manual

N/A

Logic LOW State. Force RF Change Pump to 16 mA

3

Disabled

3

Logic HIGH State

4

Enabled

4

FastLock

…

Enabled

…

FastLock

16,383

Enabled

16383

FastLock

2.8.2 RF_CPF[1:0] — FastLock Charge Pump Gain, RF Synthesizer

The RF_CPF[1:0] word is used to control the charge pump gain for the RF synthesizer when FastLock is enabled and engaged.

Four different CP gains are supported ranging from 1 to 16 mA. Note that when RF FastLock mode is disengaged or disabled the

charge pump gain is controlled by RF_CP[1:0].

RF_CPF[1:0]

Charge Pump Current

01 mA

14 mA

28 mA

316 mA

2.8.3 RF_OM[1:0] — RF Synthesizer Operating Mode

RF_OM[1:0] controls the operating mode of the RF synthesizer. The various operating modes are described below:

RF Synthesizer Operating Mode Descriptions

RF_OM

Operating Mode

Operating Mode Description

0

0

Integer

RF synthesizer always operates as an Integer N PLL

1

1

Fractional

RF synthesizer always operates as a Fractional N PLL

2

X

Reserved

Do Not use this mode

3

X

Reserved

Do Not use this mode.

Note that the Fractional Enable Bit, FE (R6[16]) needs to be set appropriately. Enabling the fractional compensation in Integer

mode always degrades performance. It is generally recommended to enable it in fractional mode, although there may be some

rare exceptions that it may be set to 0.

2.8.4 RF_CSR[1:0] — Cycle Slip Reduction Control, RF Synthesizer

RF_CSR[1:0] controls the operation of the cycle slip reduction circuitry. This circuit can be used eliminate the occurrence of phase

detector cycle slips when operating in Fractional Mode (RF_OM = 1). When operating in integer mode,the cycle slip reduction

circuitry should be disabled by setting RF_CSR = 0.

RF_CSR

CSR State

Sample Rate Reduction Factor

0

Disabled

N/A

1

Enabled

1/2

2

Enabled

1/4

3

Enabled

1/8

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