2.9 R6 REGISTER

Reg

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9876543210

DATA[20:0]

C2

C1

C0

R6

00

00000FE

0000000

PD_

M

OSC

MUX[3:0]

1

1

0

2.9.1 MUX[3:0] — Coltrol Word for the Ftest/LD Pin

The MUX[3:0] control word is used to determine the function of the Ftest/LD output pin. The pin can be setup as a general-

purpose CMOS TRI-STATE I/O pin, a digital filtered lock detect pin, an analog lock detect pin (push-pull or open drain output), or

used to view the output of the variousR&N dividers.

MUX[3:0]

Ftest/LD Output Pin Function

Output Type

0

0

0

0

Disabled

High Impedance

0

0

0

1

General Purpose I/O. Logic HIGH Output

Push-Pull

0

0

1

0

General Purpose I/O. Logic LOW Output

Push-Pull

0

0

1

1

RF & IF Analog Lock Detect (Width of

narrow low pulses determines lock)

Open-Drain

0

1

0

0

RF Analog Lock Detect (Width of narrow

low pulses determines lock)

Open-Drain

0

1

0

1

IF Analog Lock Detect (Width of narrow

low pulses determines lock)

Open-Drain

0

1

1

0

RF & IF Digital Lock Detect (High = Lock)

Push-Pull

0

1

1

1

RF Digital Lock Detect (High = Lock)

Push-Pull

1

0

0

0

IF Digital Lock Detect (High = Lock)

Push-Pull

1

0

0

1

RF & IF Analog Lock Detect (Width of

narrow low pulses determines lock)

Push-Pull

1

0

1

0

RF Analog Lock Detect (Width of narrow

low pulses determines lock)

Push-Pull

1

0

1

1

IF Analog Lock Detect (Width of narrow

low pulses determines lock)

Push-Pull

1

1

0

0

IF R Divider/2 (Output is divided by 2 to

simplify testing)

Push-Pull

1

1

0

1

IF N Divider/2 (Output is divided by 2 to

simplify testing)

Push-Pull

1

1

1

0

RF R Divider/2 (Output is divided by 2 to

simplify testing)

Push-Pull

1

1

1

1

RF N Divider/2 (Output is divided by 2 to

simplify testing)

Push-Pull

2.9.2 OSC — Single Resonator Mode

The OSC bit selects whether the oscillator input pins OSCinIF and OSCinRF drive the IF and RF R dividers separately or by a

common input signal path. When OSC is set to 0, the OSCinIF pin drives the IF R divider while the OSCinRF pin drives the RF

R divider. When the OSC bit is set to “1” the OSCinIF pin drives both the RF R and IF R counters. Note that setting the OSC mode

to “1” does not allow the use of a crystal. This part does not include the inverter for use in construction of a crystal oscillator.

2.9.3 PD_M — Power Down Mode

This bit determines if a power down event for either synthesizer will be handled synchronously or asynchronously with respect to

a charge pump event. Synchronous powerdown means that the PLL does not power down until the charge pump turns off.

Asynchronous powerdown means that the PLL powers down, regardless of the charge pump state. When set to one,

synchronous mode is enabled. When set to 0, asynchronous mode is enabled. The setting of this bit applies to both the RF & IF

synthesizers.

2.9.4 FE — Fractional Compensation Enable

For integer mode (RF_OM=0) mode, this bit should always be set to 0. For fractional mode (RF_OM = 1), this bit should be set

to 1 for the best fractional spurs. However, there may be applications using fractional mode where it would be beneficial to set

this bit to 0. Disabling this bit will drastically degrade the fractional spurs, but will also result in a small improvement in phase

noise, which may be practical for some applications.

FE

Fractional

Compensation

Circuitry

Integer

Mode

Fractional Mode

Approximate Spur

Improvement

Approximate Phase

Noise

Degradation

0

Disabled

Default State

0 dB

0 dB

1

Enabled

Illegal State

20 dB

7 dB

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