LMX2364TM datasheet(36/39 Pages) NSC

36 / 39 page

Supplemental Information (Continued)

3.3 DETERMINING THE THEORETICAL LOCK TIME

IMPROVEMENT AND FASTLOCK RESISTOR, R2

The loop bandwidth multiplier, K, is necessary in order to

determine the theoretical impact of FastLock/CSR on the

loop bandwidth and also which resistor should be switched

in parallel with the loop filter resistor R2. K = K_Kphi x

K_Fcomp where K is the loop gain multiplier K_Kphi and

K_Fcomp are the ratio of the FastLock currents and com-

parison frequencies to their steady state conditions. Note

that this should always be greater than or equal to one.

K_Fcomp is the ratio of the FastLock comparison frequency

to the steady state comparison frequency. If this ratio is less

than one, this implies that the CSR is being used.

When K is greater than one, is necessary to switch a Fast-

Lock resistor, R2’, in parallel with R2 in order to keep the

loop filter optimized and maintain the same phase margin.

After the PLL has achieved a frequency that is sufficiently

close to the desired frequency, the resistor R2’ is disengaged

and the charge pump current is and comparison frequency

are returned to normal. Of special concern is the glitch that is

caused when the resistor R2’ is disengaged. This glitch can

take up a significant portion of the lock time. The LMX2364

has enhanced switching circuitry to minimize this glitch and

therefore improve the lock time.

20050640

The change in loop bandwidth is dependent upon the loop

gain multiplier, K. The theoretical improvement in lock time is

given below, but the actual improvement will be less than this

due to the glitch that is caused by disengaging FastLock.

The theoretical improvement is given to show an upper

bound on what improvement is possible with FastLock. In

the case that K < 1, this implies the CSR is being engaged

and that the theoretical lock time will be degraded. However,

since this mode reduces or eliminates cycle slipping, the

actual lock time may be better in cases where the loop

bandwidth is small relative to the comparison frequency.

Realize that the theoretical lock time multiplier does not

account for the FastLock/CSR disengagement glitch, which

is most severe for larger values of K.

Loop Gain Multiplier,

FastLock Loop

Bandwidth/Steady

State Loop

R2’ Value

Theoretical Lock

Time Multiplier

1:8*

0.35

open

x 2.828

1:4*

0.50

open

x 2.000

1:2*

0.71

open

x 1.414

1:1

1.00

open

x 1.000

2:1

1.41

R2/0.41

x 0.707

4:1

2.00

x 0.500

8:1

2.83

R2/1.83

x 0.354

16:1

4.00

R2/3.00

x 0.250

K:1

* These modes of operation are generally not recommended

3.4 USING FASTLOCK AND CSR TO AVOID CYCLE

SLIPPING

In the case that the comparison frequency is very large ( ie.

70x)ofthe loop bandwidth, cycle slipping may occur when

an instantaneous phase error is presented to the phase

detector. This can be reduced by increasing the loop band-

width during frequency aquisition, decreasing the compari-

son frequency during frequency acquisition, or some combi-

nation of the these. If increasing the loop bandwidth during

frequency acquisition is not sufficient to reduce cycle slip-

ping, the LMX2364 also has a routine to decrease the com-

parison frequency.

LMX2364TM Datasheet(PDF) 36 Page - National Semiconductor (TI)

LMX2364TM Datasheet(HTML) 36 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL