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ICS950910 Datasheet(PDF) 13 Page - Integrated Circuit Systems

Part # ICS950910
Description  Programmable Timing Control Hub for P4
PDF  20 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS950910 Datasheet(HTML) 13 Page - Integrated Circuit Systems

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13
Integrated
Circuit
Systems, Inc.
ICS950910
0735A—03/18/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2
VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
IIH
VIN = VDD; Inputs with no pull-down
resistors
5.75
mA
IIH
VIN = VDD; Inputs with pull-down
resistors
200
µA
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5.75
mA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
µA
IDD3.3OP
CL = Full load; Select @ 100 MHz
228
156
360
mA
IDD3.3OP
CL =Full load; Select @ 133 MHz
220
159
360
mA
Powerdown Current
IDD3.3PD
IREF=2.32 mA
12
45
mA
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Clk Stabilization
1,2
TSTAB
From PowerUp or deassertion of
PowerDown to 1st clock.
2.1
ms
tPZH,tPZL
Output enable delay (all outputs)
1
12
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
12
ns
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
Delay
1
Input Capacitance
1
Input Low Current
Input High Current
Operating Supply Current



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