19

Integrated

Circuit

Systems, Inc.

ICS950910

0735A—03/18/04

Power Down Waveforms

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

VCO Internal

0ns

12

25ns

50ns

CPU 100MHz

3.3V 66MHz

PCI 33MHz

PD#

REF 14.318MHZ

48MHZ

Group Offset Waveforms

Cycl e R epeats

0ns

CPU 66MHz

CPU 100MHz

CPU 133MHz

3.5V 66MHz

PCI 33MHz

APIC 16.7MHz

REF 14.318MHz

USB 48MHz

10ns

20ns

30ns

40ns

Group Skews at Common Transition Edges

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CPU408 to CPUCS

CPU

50% to 1.25V

0

250

ps

CPU Open Drain to CPUCS

CPU

50% to 1.25V

0

75

250

CPUCS to PCI

1.25 to 1.5V

0

2.8

4

ns

CPU408 to PCI

1.25 to 1.5V

0

3.8

4

ns

AGP to PCI

1.5 to 1.5V

1.5

2.87

3.5

ns