HMC7043LP7FE datasheet(4/44 Pages) AD

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Data Sheet

HMC7043

Rev. B | Page 3 of 43

SPECIFICATIONS

VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to

+85°C) variation, as listed in Table 1.

CONDITIONS

Table 1.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE, VCC

VCC1_CLKDIST

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for CLK distribution

VCC2_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 2 and

Output Channel 3

VCC3_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 4, Output

Channel 5, Output Channel 6 and Output Channel 7

VCC4_CLKIN

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for the clock input path

VCC5_SYSREF

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for the common SYSREF divider

VCC6_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 8, Output

Channel 9, Output Channel 10, and Output Channel 11

VCC7_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 0, Output

Channel 1, Output Channel 12, and Output Channel 13

TEMPERATURE

Ambient Temperature Range, TA

−40

+25

+85

°C

1 Maximum values are guaranteed by design and characterization.

SUPPLY CURRENT

For detailed test conditions, see Table 17 and Table 18.

Table 2

Parameter1, 2

Min

Typ

Max

Unit

Test Conditions/Comments

CURRENT CONSUMPTION3

VCC1_CLKDIST

125

VCC2_OUT4

250

Typical value is given at TA = 25°C with two LVDS clocks at divide by 8

VCC3_OUT4

500

Typical value is given at 25°C with two LVDS high performance clocks,

fundamental frequency of the clock input (fO), two SYSREF clocks (off )

VCC4_CLKIN

Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input

buffer off

VCC5_SYSREF

Typical value is given at TA = 25°C with internal RF SYNC path off

VCC6_OUT4

500

Typical value is given at 25°C with two LVDS high performance clocks at

divide by 2, two SYSREF clocks (off )

VCC7_OUT4

100

500

Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF

clocks (off )

Total Current

458

1 Maximum values are guaranteed by design and characterization.

2 Currents include LVDS termination currents.

3 Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary

synchronization events.

4 Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.

This specification assumes output configurations as described in the test conditions/comments column.

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